- Author:
- WeiweiAi <wai484@aucklanduni.ac.nz>
- Date:
- 2022-05-24 10:07:05+12:00
- Desc:
- Add new experiments to expose conductances for accepting noise
- Permanent Source URI:
- https://models.physiomeproject.org/workspace/874/rawfile/14c89d8f26bf737fb7f9589aeb10dabf4ac3c186/Components/buildsrc/SMC_osc.txt
def model SMC_osc as
def import using "../cellLib/Components/units.cellml" for
unit mM using unit mM;
unit mV using unit mV;
unit uM using unit uM;
unit uM_per_s using unit uM_per_s;
enddef;
def import using "../Components/SMC.cellml" for
comp SMC using comp SMC;
enddef;
def import using "../Components/Para.cellml" for
comp Para using comp Para;
enddef;
def import using "../cellLib/Components/time.cellml" for
comp time using comp time_s;
enddef;
def comp output as
var v_i: mV {pub: in};
var s_i: uM {pub: in};
var c_i: uM {pub: in};
var w_i: dimensionless {pub: in};
var I_i: uM {pub: in};
var t: second {pub: in};
enddef;
def comp free_para as
var E: uM_per_s {init: 0, pub: out};
var J_PLCagonisti: uM_per_s {init: 0.067, pub: out};
var KCl: mM {init: 4.7, pub: out};
enddef;
def map between SMC and output for
vars v_i and v_i;
vars s_i and s_i;
vars c_i and c_i;
vars w_i and w_i;
vars I_i and I_i;
enddef;
def map between SMC and free_para for
vars E and E;
vars J_PLCagonisti and J_PLCagonisti;
vars Ko and KCl;
enddef;
def map between SMC and Para for
vars gamma and gamma;
vars vi_init and vi_init;
vars ci_init and ci_init;
vars si_init and si_init;
vars Ii_init and Ii_init;
vars F_IP3 and F_IP3;
vars K_r and K_r;
vars k and k;
vars K_Ca and K_Ca;
vars R and R;
vars F and F;
vars T and T;
vars G_Ki and G_Ki;
vars wi_init and wi_init;
vars lambda and lambda;
vars c_w and c_w;
vars v_Ca3 and v_Ca3;
vars R_K and R_K;
vars beta and beta;
vars Ki and Ki;
vars G_Cl and G_Cl;
vars v_Cl and v_Cl;
vars F_NKA and F_NKA;
vars L and L;
vars D and D;
vars v_d and v_d;
vars R_d and R_d;
vars C and C;
vars s_c and s_c;
vars c_c and c_c;
vars B and B;
vars c_b and c_b;
vars G_NCX and G_NCX;
vars v_NCX and v_NCX;
vars c_NCX and c_NCX;
vars G_Ca and G_Ca;
vars v_Ca1 and v_Ca1;
vars v_Ca2 and v_Ca2;
vars R_Ca and R_Ca;
enddef;
def map between SMC and time for
vars t and time;
enddef;
def map between output and time for
vars t and time;
enddef;
enddef;