def model MWC_18_test as
    def import using "../cellLib/Components/units.cellml" for
        unit mV using unit mV;
        unit ms using unit ms;
        unit per_ms using unit per_ms;
    enddef;

    def import using "../Components/MWC_18.cellml" for
        comp MWC_18 using comp MWC_18;
    enddef;

    def import using "../Components/Para.cellml" for
        comp Para using comp Para;
    enddef;

    def import using "../cellLib/Protocols/Patch_clamp_protocol.cellml" for
        comp sPulse_protocol_ms using comp sPulse_protocol_ms;
    enddef;

    def import using "../cellLib/Components/time.cellml" for
        comp time using comp time_ms;
    enddef;

    def comp output as
        var P_o: dimensionless {pub: in};
        var Q: dimensionless {pub: in};
        var t: ms {pub: in};
        var V: mV {pub: in};
        var dQ: per_ms {pub: in};
    enddef;

    def comp clamp_para as
        var t_ss: ms {init: 10, pub: out};
        var V_actHolding: mV {init: -20, pub: out};
        var t_act: ms {init: 100, pub: out};
        var V_actTest: mV {init: -40, pub: out};
    enddef;

    def comp free_para as
        var K: mV {init: 4.5, pub: out};
        var k_L: per_ms {init: 0.002, pub: out};
        var k_Lminus: per_ms {init: 900, pub: out};
        var f: dimensionless {init: 0.175, pub: out};
        var V0: mV {init: -20, pub: out};
    enddef;

    def map between MWC_18 and output for
        vars P_o and P_o;
        vars Q and Q;
        vars dQ and dQ;
    enddef;

    def map between MWC_18 and free_para for
        vars K and K;
        vars k_L and k_L;
        vars k_Lminus and k_Lminus;
        vars f and f;
        vars V0 and V0;
    enddef;

    def map between MWC_18 and Para for
        vars alpha and alpha;
        vars C0_init and C0_init;
        vars C1_init and C1_init;
        vars C2_init and C2_init;
        vars C3_init and C3_init;
        vars C4_init and C4_init;
        vars C5_init and C5_init;
        vars C6_init and C6_init;
        vars C7_init and C7_init;
        vars C8_init and C8_init;
        vars O0_init and O0_init;
        vars O1_init and O1_init;
        vars O2_init and O2_init;
        vars O3_init and O3_init;
        vars O4_init and O4_init;
        vars O5_init and O5_init;
        vars O6_init and O6_init;
        vars O7_init and O7_init;
        vars O8_init and O8_init;
        vars C1_i and C1_i;
        vars C2_i and C2_i;
        vars C3_i and C3_i;
        vars C4_i and C4_i;
        vars C5_i and C5_i;
        vars C6_i and C6_i;
        vars C7_i and C7_i;
        vars O1_i and O1_i;
        vars O2_i and O2_i;
        vars O3_i and O3_i;
        vars O4_i and O4_i;
        vars O5_i and O5_i;
        vars O6_i and O6_i;
        vars O7_i and O7_i;
    enddef;

    def map between MWC_18 and sPulse_protocol_ms for
        vars V and V;
    enddef;

    def map between MWC_18 and time for
        vars t and time;
    enddef;

    def map between output and sPulse_protocol_ms for
        vars V and V;
    enddef;

    def map between output and time for
        vars t and time;
    enddef;

    def map between clamp_para and sPulse_protocol_ms for
        vars t_ss and t_ss;
        vars V_actHolding and V_actHolding;
        vars t_act and t_act;
        vars V_actTest and V_actTest;
    enddef;

    def map between sPulse_protocol_ms and time for
        vars time and time;
    enddef;

enddef;